1. Field of the Invention
This invention relates generally to the operation of integrated circuits. More particularly, it relates to the generation of a power-up reset pulse for ensuring the orderly power-up of an integrated circuit.
2. Background of the Invention
When a power supply is first activated, it asserts a voltage level that rises from zero volts to a voltage level required during normal operation, for example 3.3 volts. During this "power-up" period, an integrated circuit coupled to the power supply can behave in an unknown and unpredictable manner, possibly causing the integrated circuit to function improperly once the power-up is complete. There are various causes for this improper functioning, including residual voltage on certain nodes in the integrated circuit, and delays in the distribution of the power supply signal that cause voltage differentials on transistors and other devices within the circuit. One method for preventing these problems is the application of a power-up reset pulse during the power-up period to certain critical nodes and devices with the integrated circuit.
A power-up reset pulse preferably has a voltage level that starts at zero volts, rises linearly until a certain predetermined level is achieved, and then drops back down to zero volts. During the rising period, the voltage level of the power-up reset pulse should be as identical as possible to the rising voltage level asserted by the power supply. The reset pulse is applied to key nodes and devices throughout the integrated circuit being powered up so that the voltage level at these points is substantially predictable throughout the power-up period. Once power-up is complete, any circuitry used to generate the power-up reset pulse becomes inactive.
Previous power-up reset circuits for generating a power-up reset pulse utilized resistive and capacitive elements combined to create a desired ramp shape. These circuits have several shortcomings. The capacitive element normally requires a certain amount of time after the power supply is removed to discharge before another reset pulse can be generated. However, a typical method for resetting a computer or other system using integrated circuits is to turn the system off and then back on again quickly. Accordingly, the need to discharge the capacitor prior to reactivating the system creates a delay and inconvenience for the user. Additionally, the resistive element of previous power-up reset circuit continues to cause the circuit to drain DC current even after the circuit is no longer operating. With the advent to laptop computers which rely on batteries for power, and the emergence of an environmentally friendly computer market, the unnecessary current drain is another shortcoming. Furthermore, both resistive and capacitive elements in integrated circuits are extremely sensitive to process and temperature parameters. Accordingly, the voltage level at which the reset pulse falls to zero deassertion voltage of previous power-up reset circuits can vary considerably. It is generally desirable to maintain predictability within an integrated circuit, and any sensitivity to process and temperature parameters may affect the predictability of the integrated circuit.